View MB90F822A_2750910.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-13738-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90820 series mb90822/823/f822a/f823a/v820 description the mb90820 series is a line of general-purpose, fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-tim e processing, such as consumer products. while inheriting the at architecture of the f 2 mc* family, the instruction set for the f 2 mc-16lx cpu core of the mb90820 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90820 series has an on-chip 32-bit accumulator which enables processing of long-word data. the peripheral resources integrated in the mb90820 series include : an 8/10-bit a/d converter, 8-bit d/a convert- ers, uarts (sci) 0, 1, multi-functional timer (16-bit free- running timer, input capture units (icus) 0 to 3, output compare units (ocus) 0 to 5, 16-bit ppg timer 0, wave form generator), 16-bit ppg timer 1, 2, pwc 0, 1, 16-bit reload timer 0, 1 and dtp/external interrupt. *: f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. features ? minimum execution time of instruction : 42 ns / 4 mhz oscillation (uses pll clock multiplication) maximum multiplier = 6 maximum memory space 16m bytes linear/bank access (continued) packages 80-pin plastic qfp 80-pin plastic lqfp 80-pin plastic lqfp (fpt-80p-m06) (fpt-80p-m05) (fpt-80p-m11)
mb90820 series 2 (continued) instruction set optimized for controller applications supported data types : bit, byte, word, and long-word types standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations enhanced multiplication/division and reti instructions enhanced high level language (c) and multi-tasking support instructions use of a system stack pointer symmetrical instruction set and barrel shift instructions program patch function (for two address pointers) increased execution speed : 4-byte instruction queue powerful interrupt function up to eight priority levels programmable external interrupt inputs : 8 channels automatic data transmission func tion independent of cpu operation up to 16 channels for the ex tended intelligent i/o service dtp request inputs : 8 channels internal rom flash memory : 64k/128k bytes with flash security mask rom : 64k/128k bytes internal ram eva : 16k bytes flash memory : 4k bytes mask rom : 4k bytes general-purpose ports up to 66 channels (pull-up resistor settable port for : 32 channels) a/d converter (rc) : 16 channels 8/10-bit resolution selectable conversion time : min 3 s (24 mhz operation, including sampling time) 8-bit d/a converter : 2 channels uart : 2 channels 16-bit ppg timer : 3 channels mode switching function provi ded (pwm mode or one-shot mode) ch0 can be worked with multi-functional timer or independently 16-bit reload timer : 2 channels 16-bit pwc timer : 2 channels multi-functional timer input capture : 4 channels output compare with selectable buffer : 6 channels free-running timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit ppg timer : 1 channel waveform generator : (16-bit timer : 3 c hannels, 3-phase waveform or dead time) timebase counter/watchdog timer : 18-bit low-power consumption mode : sleep mode stop mode cpu intermittent operation mode (continued)
mb90820 series 3 (continued) package : lqfp-80 (fpt-80p-m05 : 0.50 mm pitch) lqfp-80 (fpt-80p-m11 : 0.65 mm pitch) qfp-80 (fpt-80p-m06 : 0.80 mm pitch) cmos technology
mb90820 series 4 product lineup (continued) mb90v820 MB90F822A mb90f823a mb90822 mb90823 classification evaluation product flash memory product with flash security mask rom product rom size ? 64k bytes 128k bytes 64k bytes 128k bytes ram size 16k bytes 4k bytes cpu function number of instruction : 351 minimum execution time : 42 ns / 4 mhz (pll 6) addressing mode : 23 data bit length : 1, 8, 16 bits maximum memory space: 16m bytes i/o port i/o port (cmos) : 66 pwc pulse width counter timer : 2 channels timer function (select the counter timer from three internal clocks) various pulse width measuring function (?h? pulse width, ?l? pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) uart uart : 2 channels with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized transmission (with start and stop bits) can be selected and used. transmission can be one-to-one (bidirectional co mmunication) or one-to-n (master-slave com- munication). 16-bit reload timer reload timer : 2 channels reload mode, single-shot mode or event count mode selectable 16-bit ppg timer ppg timer : 3 channels pwm mode or single-shot mode selectable ch0 can be worked with multi-fu nctional timer or independently. multi-functional timer (for ac/dc motor control) 16-bit free-running timer with up or up- down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit ppg timer : 1 channel waveform generator (16-bit timer : 3 ch annels, 3-phase waveform or dead time) 8/10-bit a/d converter 8/10-bit resolution (16 channels) conversion time : min 3 s (24 mhz internal clock, including sampling time) 8-bit d/a converter 8-bit resolution (2 channels) dtp/external interrupt 8 independent channels interrupt factors : rising edge, falling edge, ?l? level or ?h? level low-power consumption stop mode / sleep mode / cpu intermittent operation mode part number item
mb90820 series 5 (continued) *1 : mb90v820 is operating guaranteed temperature 0 c to + 25 c. *2 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. package and corresponding products : available x : not available note: for more information about each package, see ? package dimensions?. mb90v820 MB90F822A mb90f823a mb90822 mb90823 package pga-299 lqfp-80 (fpt-80p-m05 : 0.50 mm pitch) lqfp-80 (fpt-80p-m11 : 0.65 mm pitch) qfp-80 (fpt-80p-m06 : 0.80 mm pitch) power supply voltage for operation* 1 4.5 v to 5.5 v* 1 3.5 v to 5.5 v : normal operation when a/d converter and d/a converter are not used 4.0 v to 5.5 v : normal operation when d/a converter is not used 4.5 v to 5.5 v : normal operation when a/d converter and d/a converter are used process cmos emulator power supply* 2 included ? package mb90v820 MB90F822A mb90f823a mb90822 mb90823 pga-299 xxxx fpt-80p-m05 x fpt-80p-m11 x fpt-80p-m06 x part number item
mb90820 series 6 differences among products memory size in evaluation with an evaluation product, note the di fference between the evaluation product and the product actually used. the following items must be taken into consideration. the mb90v820 does not have an internal rom, howeve r, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool , enabling selection of rom size by settings of the development tool. in the mb90v820, images from ff8000 h to ffffff h are mapped to bank 00, and fe0000 h to ff7fff h are mapped to bank fe and bank ff only. (this setting can be changed by configuring the development tool.) in the mb90822/f822a, images from ff8000 h to ffffff h are mapped to bank 00, and ff0000 h to ff7fff h are mapped to bank ff only. in th e mb90823/f823a, images from ff8000 h to ffffff h are mapped to bank 00, and fe0000 h to ff7fff h are mapped to bank fe and bank ff only.
mb90820 series 7 pin assignment (continued) * : high current pin. avr avcc avss p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 p51/int7 p50/ppg2 p47/pwo1 p46/pwi1 p45/sin0 p44/sot0 p43/sck0 rst p42/to0 p41/tin0 vss x0 x1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 md0 md1 md2 p40/ppg1 p37/ppg0 p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 c vss vcc p00 * p01 * p02 * p03 * p04 * p05 * p06/pwi0 * p07/pwo0 * p10/int0/dtti p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17 p20/tin1 p21/to1 p22 vcc p23 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p70/da0/an8 p71/da1/an9 p72/sin1/an10 p73/sot1/an11 p74/sck1/an12 p75/frck/an13 p76/in0/an14 p77/in1/an15 p80/in2 p81/in3 p82/rto0(u) * p83/rto1(x) * p84/rto2(v) * p85/rto3(y) * p86/rto4(w) * p87/rto5(z) * 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 (top view) (fpt-80p-m06)
mb90820 series 8 (continued) * : high current pin. avss p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 p51/int7 p50/ppg2 p47/pwo1 p46/pwi1 p45/sin0 p44/sot0 p43/sck0 rst p42/to0 p41/tin0 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x0 x1 md0 md1 md2 p40/ppg1 p37/ppg0 p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 p23 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vcc p00 * p01 * p02 * p03 * p04 * p05 * p06/pwi0 * p07/pwo0 * p10/int0/dtti p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17 p20/tin1 p21/to1 p22 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avcc avr p70/da0/an8 p71/da1/an9 p72/sin1/an10 p73/sot1/an11 p74/sck1/an12 p75/frck/an13 p76/in0/an14 p77/in1/an15 p80/in2 p81/in3 p82/rto0(u) * p83/rto1(x) * p84/rto2(v) * p85/rto3(y) * p86/rto4(w) * p87/rto5(z) * c vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (top view) (fpt-80p-m11) (fpt-80p-m05)
mb90820 series 9 pin description (continued) pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 21, 22 23, 24 x0,x1 a oscillating oscillation pins. 17 19 rst b reset input external reset input pin. 59 to 54 61 to 56 p00 to p05 c port input general-purpose i/o ports. 53 55 p06 c general-purpose i/o ports. pwi0 pwc ch0 signal input pin. 52 54 p07 c general-purpose i/o ports. pwo0 pwc ch0 signal output pin. 51 53 p10 d general-purpose i/o ports. int0 external interrupt request input ch0 pin. dtti rto0 to rto5 pins for fixed-level input. this func- tion is enabled when the waveform generator speci- fies its input bits. 50 to 45 52 to 47 p11 to p16 d general-purpose i/o ports. int1 to int6 external interrupt request input ch1 to ch6 pins. 44 46 p17 d general-purpose i/o ports. 43 45 p20 d general-purpose i/o ports. tin1 external clock input pin for reload timer ch1. 42 44 p21 d general-purpose i/o ports. to1 event output pin for reload timer ch1. 41, 39 to 35 43, 41 to 37 p22 to p27 d general-purpose i/o ports. 34 to 28 36 to 30 p30 to p3 6 e general-purpose i/o ports. 27 29 p37 e general-purpose i/o ports. ppg0 output pins for ppg timer ch0. 26 28 p40 f general-purpose i/o ports. ppg1 output pins for ppg timer ch1. 19 21 p41 f general-purpose i/o ports. tin0 external clock input pin for reload timer ch0. 18 20 p42 f general-purpose i/o ports. to0 event output pin for reload timer ch0. *1: fpt-80p-m05, fpt-80p-m11 *2: fpt-80p-m06 *3: see ? i/o circuit type?.
mb90820 series 10 (continued) pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 16 18 p43 f port input general-purpose i/o ports. sck0 serial clock i/o pin for uart ch0. 15 17 p44 f general-purpose i/o ports. sot0 serial data output pin for uart ch0. 14 16 p45 g general-purpose i/o ports. sin0 serial data input pin for uart ch0. 13 15 p46 f general-purpose i/o ports. pwi1 pwc ch1 signal input pin. 12 14 p47 f general-purpose i/o ports. pwo1 pwc ch1 signal output pin. 11 13 p50 f general-purpose i/o ports. ppg2 output pins for ppg timer ch2. 10 12 p51 f general-purpose i/o ports. int7 external interrupt request input ch7 pin. 9 to 2 11 to 4 p60 to p67 h analog input general-purpose i/o ports. an0 to an7 a/d converter analog input pins. 78, 77 80, 79 p70, p71 i general-purpose i/o ports. da0, da1 d/a converter analog output pins. an8, an9 a/d converter analog input pins. 76 78 p72 j general-purpose i/o ports. sin1 serial data input pin for uart ch1. an10 a/d converter analog input pins. 75 77 p73 k general-purpose i/o ports. sot1 serial data output pin for uart ch1. an11 a/d converter analog input pins. 74 76 p74 k general-purpose i/o port. sck1 serial clock i/o pin for uart ch1. an12 a/d converter analog input pins. 73 75 p75 k general-purpose i/o ports. frck external clock input pin for free-running timer. an13 a/d converter analog input pins. *1: fpt-80p-m05, fpt-80p-m11 *2: fpt-80p-m06 *3: see ? i/o circuit type?.
mb90820 series 11 (continued) pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 72, 71 74, 73 p76, p77 k analog input general-purpose i/o ports. in0, in1 trigger input pins fo r input capture ch0, ch1. an14, an15 a/d converter analog input pins. 70, 69 72, 71 p80, p81 f port input general-purpose i/o ports. in2, in3 trigger input pins fo r input capture ch2, ch3. 68 to 63 70 to 65 p82 to p87 l general-purpose i/o ports. rto0 (u) to rto5 (z) waveform generator output pins. these pins output the waveforms specified at the waveform generator. output is generated when waveform generator output is enabled. 25 27 md2 m mode input input pin for operati on mode specification. 24, 23 26, 25 md1, md0 n input pin fo r operation mode specification. 80 2 av cc ? ? analog power supply pin. 79 1 avr ? vref + pin for the a/d converter. vref - is fixed to avss internally. 13av ss ? analog power supply (ground) pin. 20, 61 22, 63 vss ? ? power (ground) pin. 40, 60 42, 62 vcc ? power pin. 62 64 c ? ? connect pin for smoothing capacitor to stabilize in- ternal power supply. *1: fpt-80p-m05, fpt-80p-m11 *2: fpt-80p-m06 *3: see ? i/o circuit type?.
mb90820 series 12 i/o circuit type (continued) classification type remarks a main clock (main clock crystal oscillator) oscillation feedback resistor : approx. 1 m ? b hysteresis input pull-up resistor : approx. 50 k ? c cmos output hysteresis input selectable pull-up resistor : approx. 50 k ? i ol = 12 ma d cmos output hysteresis input selectable pull-up resistor : approx. 50 k ? i ol = 4 ma e cmos output cmos input with pull-up control i ol = 4 ma x1 x0 p-ch n-ch clock input standby control signal r p-ch n-ch r p-ch digital output pull-up control hysteresis input digital output standby mode control p-ch n-ch r p-ch digital output pull-up control hysteresis input digital output standby mode control p-ch n-ch r p-ch digital output pull-up control cmos input digital output standby mode control
mb90820 series 13 (continued) classification type remarks f cmos output hysteresis input i ol = 4 ma g cmos output hysteresis input cmos input (selectable for uart ch0 data input pin) i ol = 4 ma h cmos output cmos input analog input i ol = 4 ma i cmos output hysteresis input analog output analog input i ol = 4 ma p-ch n-ch digital output hysteresis input digital output standby mode control p-ch n-ch digital output hysteresis input digital output standby mode control cmos input p-ch n-ch pout cmos input nout analog input control analog input p-ch n-ch digital output hysteresis input digital output analog i/o control analog output analog input
mb90820 series 14 (continued) classification type remarks j cmos output hysteresis input cmos input (selectable for uart ch1 data input pin) i ol = 4 ma k cmos output hysteresis input analog input i ol = 4 ma l cmos output hysteresis input i ol = 12 ma m mask rom / evaluation product hysteresis input pull-down resistor : approx. 50 k ? flash memory product cmos input no pull-down resistor n mask rom / evaluation product hysteresis input flash memory product cmos input p-ch n-ch digital output hysteresis input digital output analog input control cmos input analog input p-ch n-ch digital output hysteresis input digital output analog input control analog input p-ch n-ch digital output hysteresis input digital output standby mode control r
mb90820 series 15 handling devices special care is required for the fo llowing when handling the device : preventing latch-up stabilization of supply voltage treatment of unused pins using external clock power supply pins (v cc /v ss ) pull-up/pull-down resistors crystal oscillator circuit turning-on sequence of power supply to a/d co nverter and d/a converte r, and analog inputs connection of unused pins of a/d converter and d/a converter if a/d converter and d/a converter are unused notes on energization notes on during operation of pll clock mode 1. preventing latch-up cmos ic chips may suffer latch- up under the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rate d voltage is applied between v cc and v ss . the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dr astically, causing thermal damage to the device. in using the devices, take sufficient care to avoid exceeding maximum ratings. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avr) exceed the digital power-supply voltage. 2. stabilization of supply voltage a sudden change in the supply voltage may cause the device to malfunct ion even within the specified v cc supply voltage operation range. therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak-to-peak values) at commercial frequencies (50 hz to 60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ ms at instantaneous power switching. 3. treatment of unused pins leaving unused input pins open may result in misbeha vior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output stat e and can be left open, or the input state with the above described connection. 4. using external clock to use external clock, drive the x0 pin and leave x1 pin open. x 0 x 1 mb90820 series open
mb90820 series 16 5. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioni ng of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss to the device from the current supply source at a low impedance. as a measure against power supply no ise, connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss in the vicinity of v cc and v ss pins of the device. 6. pull-up/pull-down resistors the mb90820 series does not support internal pull-up/pull-do wn resistors option (port 0 to port 3 : built-in pull- up resistors) . use extern al components where needed. 7. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, cr ystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you design a printed circuit board. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. 8. turning-on sequence of power supply to a/d converter and d/a converter, and analog inputs make sure to turn on the a/d converter po wer supply, d/a converter power supply (av cc , avrh, avr) and analog inputs (an0 to an15) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter power supply, d/a converter power supply, and analog inputs. in this case, make sure that the voltage not exceed avr or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable). 9. connection of unused pins of a/d converter and d/a converter if a/d converter and d/a converter are unused connect unused pins of a/d conv erter and d/a converter to av cc = v cc , av ss = avrh = avrl = v ss . 10. notes on energization to prevent the internal regulator circuit from malfunct ioning, set the voltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90820 series
mb90820 series 17 11. notes on during operation of pll clock mode if the pll clock mode is selected, the microcontroller atte mpts to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed.
mb90820 series 18 block diagram x0 rst ram rom 6 note : p00 to p07, p10 to p17, p20 to p27 and p30 to p37: wi th build-in resistors that can be used as input pull-up resistors. * : high current drive pin. f 2 mc-16lx bus clock control interrupt controller dtp/external interrupt circuit cmos i/o port 1, 2, 4, 5, 7 cmos i/o port 6 cmos i/o port 0, 1, 3, 7, 8 rom correction rom mirroring p82/rto0 (u) * p83/rto1 (x) * p84/rto2 (v) * p85/rto3 (y) * p86/rto4 (w) * p87/rto5 (z) * p10/int0/dtti p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 cpu f 2 mc-16lx core delayed interrupt generator timebase timer avr av cc av ss a/d converter 16 (8/10-bit) reset circuit (watchdog timer) vss 2, vcc 2, md0 to md2, c other pins 16-bit ppg timer (ch0) 16-bit input capture (ch0 to ch3) 16-bit free-running timer 16-bit output (ch0 to ch5) compare waveform generator multi-functional timer 4 p76/in0/an14 p77/in1/an15 p80/in2 p81/in3 p75/frck/an13 uart (ch0) 8 x1 4 16-bit ppg (ch1) 16-bit reload timer (ch0) p45/sin0 p44/sot0 p43/sck0 pwc (ch1) p46/pwi1 p47/pwo1 p37/ppg0 p42/to0 p41/tin0 p40/ppg1 p16/int6 to p11/int1 p51/int7 uart (ch1) p72/sin1/an10 p73/sot1/an11 p74/sck1/an12 16-bit ppg (ch2) p50/ppg2 16-bit reload timer (ch1) p21/to1 p20/tin1 7 p30 to p36 pwc (ch0) p06/pwi0 * p07/pwo0 * 6 p00 to p05 * p17 6 p22 to p27 8-bit d/a converter p70/da0/an8 p71/da1/an9 cmos i/o port 7
mb90820 series 19 memory map note: the rom data of bank ff is refl ected to the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit is assigned to th e same address, enabling reference of the table on the rom without stating ?far?. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom ar ea of the ff bank exceeds 32k bytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff8000 h to ffffff h looks, therefore, as if it were the image for 008000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff8000 h to ffffff h . ffffff h 010000 h 000100 h 0000f0 h 000000 h 0000ff h 0000ef h address #1 - 1 h address #1 00ffff h address #2 - 1 h address #2 address #3 address #3 + 1 h rom area rom area* (ff bank image) ram area register peripheral area : internal access memo ry : access not allowed parts no. address#1 address#2 address#3 mb90822 ff0000 h 008000 h 0010ff h mb90823 fe0000 h 008000 h 0010ff h MB90F822A ff0000 h 008000 h 0010ff h mb90f823a fe0000 h 008000 h 0010ff h mb90v820 (fe0000 h ) 008000 h 0040ff h * : in single chip mode, the mirror function is supported.
mb90820 series 20 f 2 mc-16lx cpu programming model dedicated registers ah al usp ssp ps pc dpr pcb dtb usb ssb adb 8 bit 16 bit 32 bit : accumulator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a sequence of 32-bit register. : user stack pointer (usp) the 16-bit pointer indicati ng the user stack address. : system stack pointer (ssp) the 16-bit pointer indicating the system stack address. : processor status (ps) the 16-bit register indicating the system status. : program counter (pc) the 16-bit register indicating storing location of the current instruction code. : direct page register (dpr) the 8-bit register indicating bit 8 through 15 of the operand address in executing of the short direct addressing. : program bank register (pcb) the 8-bit register indicating the program space. : data bank register (dtb) the 8-bit register indicating the data space. : user stack bank register (usb) the 8-bit register indicating the user stack space. : system stack bank register (ssb) the 8-bit register indicati ng the system stack space. : additional data bank register (adb) the 8-bit register indicating the additional
mb90820 series 21 general-purpose registers processor status (ps) r7 r6 r5 r4 r3 r2 r1 rw3 rw2 rw1 rw0 16-bit r0 rw7 rw6 rw5 rw4 rl 3 rl 2 rl 1 rl 0 0 00180 h + (rp 10 h ) maximum of 32 banks bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 ilm rp ccr bit 3 bit 2 bit 1 bit 0 ilm2 ps ilm1 ilm0 b4 b3 b2 b1 b0 ? istnzvc 00000000 ? 0 1xxxxx i nitial value : unused x : undefined ?
mb90820 series 22 i/o map (continued) address abbreviation register byte ac- cess word access resource name initial value 000000 h pdr0 port 0 data register r/w r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w r/w port 8 xxxxxxxx b 000009 h to 00000f h prohibited area 000010 h ddr0 port 0 data direction register r/w r/w port 0 0 00 00 00 0 b 000011 h ddr1 port 1 data direction register r/w r/w port 1 0 00 00 00 0 b 000012 h ddr2 port 2 data direction register r/w r/w port 2 0 00 00 00 0 b 000013 h ddr3 port 3 data direction register r/w r/w port 3 0 00 00 00 0 b 000014 h ddr4 port 4 data direction register r/w r/w port 4 0 00 00 00 0 b 000015 h ddr5 port 5 data direction register r/w r/w port 5 xxxxxx00 b 000016 h ddr6 port 6 data direction register r/w r/w port 6 0 00 00 00 0 b 000017 h ddr7 port 7 data direction register r/w r/w port 7 0 00 00 00 0 b 000018 h ddr8 port 8 data direction register r/w r/w port 8 0 00 00 00 0 b 000019 h to 00001f h prohibited area 000020 h smr0 serial mode register ch0 r/w r/w uart ch0 00000000 b 000021 h scr0 serial control register ch0 w, r/w w, r/w 0 00 00 10 0 b 000022 h sidr0 / sodr0 serial input data register ch0 / serial output data register ch0 r/w r/w xxxxxxxx b 000023 h ssr0 serial status register ch0 r, r/w r, r/w 0 00 01 00 0 b 000024 h smr1 serial mode register ch1 r/w r/w uart ch1 00000000 b 000025 h scr1 serial control register ch1 w, r/w w, r/w 0 00 00 10 0 b 000026 h sidr1 / sodr1 serial input data register ch1 / serial output data register ch1 r/w r/w xxxxxxxx b 000027 h ssr1 serial status register ch1 r, r/w r, r/w 0 00 01 00 0 b 000028 h pwcsl1 pwc control status register ch1 r/w r/w pwc timer ch1 00000000 b 000029 h pwcsh1 r, r/w r, r/w 0 00 00 00 0 b 00002a h pwc1 pwc data buffer register ch1 ? r/w xxxxxxxx b 00002b h xxxxxxxx b 00002c h div1 divide ratio control register ch1 r/w r/w xxxxxx00 b
mb90820 series 23 (continued) address abbrevia- tion register byte ac- cess word ac- cess resource name initial value 00002d h , 00002e h prohibited area 00002f h pckcr pll clock control register w w pll xxxx0000 b 000030 h enir dtp / interrupt enable register r/w r/w dtp/ external interrupt ch0 to ch7 00000000 b 000031 h eirr dtp / interrupt cause register r/w r/w xxxxxxxx b 000032 h elvrl request level setting register (lower byte) r/w r/w 00000000 b 000033 h elvrh request level setting register (higher byte) r/w r/w 00000000 b 000034 h prohibited area 000035 h cdcr0 clock division ratio control register ch0 r/w r/w communication prescaler ch0 00xxx000 b 000036 h prohibited area 000037 h cdcr1 clock division ratio control register ch1 r/w r/w communication prescaler ch1 00xxx000 b 000038 h pdcr0 ppg down counter register ch0 ? r 16-bit ppg timer ch0 11111111 b 000039 h 11111111 b 00003a h pcsr0 ppg period setting register ch0 ? w xxxxxxxx b 00003b h xxxxxxxx b 00003c h pdut0 ppg duty setting register ch0 ? w xxxxxxxx b 00003d h xxxxxxxx b 00003e h pcntl0 ppg control status register ch0 r/w r/w xx000000 b 00003f h pcnth0 r/w r/w 00000000 b 000040 h pdcr1 ppg down counter register ch1 ? r 16-bit ppg timer ch1 11111111 b 000041 h 11111111 b 000042 h pcsr1 ppg period setting register ch1 ? w xxxxxxxx b 000043 h xxxxxxxx b 000044 h pdut1 ppg duty setting register ch1 ? w xxxxxxxx b 000045 h xxxxxxxx b 000046 h pcntl1 ppg control status register ch1 r/w r/w xx000000 b 000047 h pcnth1 r/w r/w 00000000 b 000048 h pdcr2 ppg down counter register ch2 ? r 16-bit ppg timer ch2 11111111 b 000049 h 11111111 b 00004a h pcsr2 ppg period setting register ch2 ? w xxxxxxxx b 00004b h xxxxxxxx b 00004c h pdut2 ppg duty setting register ch2 ? w xxxxxxxx b 00004d h xxxxxxxx b 00004e h pcntl2 ppg control status register ch2 r/w r/w xx000000 b 00004f h pcnth2 r/w r/w 00000000 b
mb90820 series 24 (continued) address abbreviation register byte access word access resource name initial value 000050 h tmrr0 16-bit timer register ch0 ? r/w waveform generator xxxxxxxx b 000051 h xxxxxxxx b 000052 h tmrr1 16-bit timer register ch1 ? r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmrr2 16-bit timer register ch2 ? r/w xxxxxxxx b 000055 h xxxxxxxx b 000056 h dtcr0 16-bit timer control register ch0 r/w r/w 0 00 0 00 00 b 000057 h dtcr1 16-bit timer control register ch1 r/w r/w 0 00 0 00 00 b 000058 h dtcr2 16-bit timer control register ch2 r/w r/w 0 00 0 00 00 b 000059 h sigcr waveform control register r/w r/w 0 00 0 00 00 b 00005a h cpclrb / cpclr compare clear buffer register/ compare clear register ? r/w 16-bit free-running timer 11111111 b 00005b h 11111111 b 00005c h tcdt timer data register ? r/w 00000000 b 00005d h 00000000 b 00005e h tccsl timer control status register (lower) r/w r/w 16-bit free-running timer x0000000 b 00005f h tccsh timer control status register (upper) r/w r/w 00000000 b 000060 h ipcp0 input capture data register ch0 ? r 16-bit input capture (ch0 to ch3) xxxxxxxx b 000061 h xxxxxxxx b 000062 h ipcp1 input capture data register ch1 ? r xxxxxxxx b 000063 h xxxxxxxx b 000064 h ipcp2 input capture data register ch2 ? r xxxxxxxx b 000065 h xxxxxxxx b 000066 h ipcp3 input capture data register ch3 ? r xxxxxxxx b 000067 h xxxxxxxx b 000068 h picsl01 input capture control status register ch0,ch1 (lower) r/w r/w 00000000 b 000069 h picsh01 ppg output control / input capture control status register ch0,ch1 (upper) r/w r/w 00000000 b 00006a h icsl23 input capture control status register ch2,ch3 (lower) r/w r/w 00000000 b 00006b h icsh23 input capture control status register ch2,ch3 (upper) r r xxxxxx00 b 00006c h to 00006e h prohibited area
mb90820 series 25 (continued) address abbreviation register byte access word access resource name initial value 00006f h romm rom mirroring function selection register ww rom mirroring function xxxxxxx1 b 000070 h occpb0 / occp0 output compare buffer register / output compare register ch0 ? r/w output compare (ch0 to ch5) xxxxxxxx b 000071 h xxxxxxxx b 000072 h occpb1 / occp1 output compare buffer register / output compare register ch1 ? r/w xxxxxxxx b 000073 h xxxxxxxx b 000074 h occpb2 / occp2 output compare buffer register / output compare register ch2 ? r/w xxxxxxxx b 000075 h xxxxxxxx b 000076 h occpb3 / occp3 output compare buffer register / output compare register ch3 ? r/w xxxxxxxx b 000077 h xxxxxxxx b 000078 h occpb4 / occp4 output compare buffer register / output compare register ch4 ? r/w xxxxxxxx b 000079 h xxxxxxxx b 00007a h occpb5 / occp5 output compare buffer register / output compare register ch5 ? r/w xxxxxxxx b 00007b h xxxxxxxx b 00007c h ocs0 compare control register ch0 r/w r/w 0 00 01 10 0 b 00007d h ocs1 compare control register ch1 r/w r/w x 1 10 00 00 b 00007e h ocs2 compare control register ch2 r/w r/w 0 00 01 10 0 b 00007f h ocs3 compare control register ch3 r/w r/w x 1 10 00 00 b 000080 h ocs4 compare control register ch4 r/w r/w 0 00 01 10 0 b 000081 h ocs5 compare control register ch5 r/w r/w x 1 10 00 00 b 000082 h tmcsrl0 timer control status register ch0 (lower) r/w r/w 16-bit reload timer (ch0) 00000000 b 000083 h tmcsrh0 timer control status register ch0 (upper) r/w r/w xxx10000 b 000084 h tmr0 / tmrd0 16 bit timer register ch0 / 16-bit reload register ch0 ? r/w xxxxxxxx b 000085 h xxxxxxxx b 000086 h tmcsrl1 timer control status register ch1 (lower) r/w r/w 16-bit reload timer (ch1) 00000000 b 000087 h tmcsrh1 timer control status register ch1 (upper) r/w r/w xxx10000 b 000088 h tmr1 / tmrd1 16 bit timer register ch1 / 16-bit reload register ch1 ? r/w xxxxxxxx b 000089 h xxxxxxxx b 00008a h , 00008b h prohibited area 00008c h rdr0 port 0 pull-up resistor setting register r/w r/w port 0 00000000 b 00008d h rdr1 port 1 pull-up resistor setting register r/w r/w port 1 00000000 b
mb90820 series 26 (continued) address abbreviation register byte ac- cess word access resource name initial value 00008e h rdr2 port 2 pull-up resistor setting register r/w r/w port 2 00000000 b 00008f h rdr3 port 3 pull-up resistor setting register r/w r/w port 3 00000000 b 000090 h to 00009d h prohibited area 00009e h pacsr program address detection control status register r/w r/w address match detection xxxx0000 b 00009f h dirr delayed interrupt cause / clear register r/w r/w delayed interrupt xxxxxxx0 b 0000a0 h lpmcr low-power consumption mode control register w, r/w w, r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r, r/w r, r/w 1 11 11 10 0 b 0000a2 h to 0000a7 h prohibited area 0000a8 h wdtc watchdog timer control register r, r/w r, r/w watchdog timer xxxxx111 b 0000a9 h tbtc timebase timer control regist er w, r/w w, r/w timebase timer 1 xx0 0 10 0 b 0000aa h to 0000ad h prohibited area 0000ae h fmcs flash memory control status register r, r/w r, r/w flash memory interface circuit 000x0000 b 0000af h prohibited area 0000b0 h icr00 interrupt control register 00 r/w r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w r/w 0 00 00 11 1 b 0000b2 h icr02 interrupt control register 02 r/w r/w 0 00 00 11 1 b 0000b3 h icr03 interrupt control register 03 r/w r/w 0 00 00 11 1 b 0000b4 h icr04 interrupt control register 04 r/w r/w 0 00 00 11 1 b 0000b5 h icr05 interrupt control register 05 r/w r/w 0 00 00 11 1 b 0000b6 h icr06 interrupt control register 06 r/w r/w 0 00 00 11 1 b 0000b7 h icr07 interrupt control register 07 r/w r/w 0 00 00 11 1 b 0000b8 h icr08 interrupt control register 08 r/w r/w 0 00 00 11 1 b 0000b9 h icr09 interrupt control register 09 r/w r/w 0 00 00 11 1 b 0000ba h icr10 interrupt control register 10 r/w r/w 0 00 00 11 1 b 0000bb h icr11 interrupt control register 11 r/w r/w 0 00 00 11 1 b 0000bc h icr12 interrupt control register 12 r/w r/w 0 00 00 11 1 b 0000bd h icr13 interrupt control register 13 r/w r/w 0 00 00 11 1 b 0000be h icr14 interrupt control register 14 r/w r/w 0 00 00 11 1 b 0000bf h icr15 interrupt control register 15 r/w r/w 0 00 00 11 1 b
mb90820 series 27 (continued) meaning of abbreviations used for reading and writing r/w: read and write enabled r : read-only w : write-only explanation of initial values 0 : the bit is initialized to ?0?. 1 : the bit is initialized to ?1?. x : the initial value of the bit is undefined. address abbrevia- tion register byte ac- cess word access resource name initial value 0000c0 h pwcsl0 pwc control status register ch0 r/w r/w pwc timer (ch0) 00000000 b 0000c1 h pwcsh0 r, r/w r, r/w 0 00 00 00 0 b 0000c2 h pwc0 pwc data buffer register ch0 ? r/w xxxxxxxx b 0000c3 h xxxxxxxx b 0000c4 h div0 divide ratio control register ch0 r/w r/w xxxxxx00 b 0000c5 h ader0 a/d input enable register 0 r/w r/w port 6, a/d 1 11 11 11 1 b 0000c6 h adcs0 a/d control status register 0 r/w r/w 8/10-bit a/d converter 000xxxx0 b 0000c7 h adcs1 a/d control status register 1 w, r/w w, r/w 00 00 00 0 x b 0000c8 h adcr0 a/d data register 0 r r xxxxxxxx b 0000c9 h adcr1 a/d data register 1 r r xxxxxxxx b 0000ca h adsr0 a/d setting register 0 r/w r/w 0 00 00 00 0 b 0000cb h adsr1 a/d setting register 1 r/w r/w 0 00 00 00 0 b 0000cc h dat0 d/a data register 0 r/w r/w 8-bit d/a converter xxxxxxxx b 0000cd h dat1 d/a data register 1 r/w r/w xxxxxxxx b 0000ce h dacr0 d/a control register 0 r/w r/w xxxxxxx0 b 0000cf h dacr1 d/a control register 1 r/w r/w xxxxxxx0 b 0000d0 h ader1 a/d input enable register 1 r/w r/w port 7, a/d 1 11 11 11 1 b 0000d1 h to 0000ef h prohibited area 0000f0 h to 0000ff h external area 001ff0 h padrl0 program address detection register 0 (lower) r/w r/w address match detection xxxxxxxx b 001ff1 h padrm0 program address detection register 0 (middle) r/w r/w xxxxxxxx b 001ff2 h padrh0 program address detection register 0 (higher) r/w r/w xxxxxxxx b 001ff3 h padrl1 program address detection register 1 (lower) r/w r/w xxxxxxxx b 001ff4 h padrm1 program address detection register 1 (middle) r/w r/w xxxxxxxx b 001ff5 h padrh1 program address detection register 1 (higher) r/w r/w xxxxxxxx b
mb90820 series 28 interrupt factors, interrupt vectors, interrupt control register : can be used and support the ei 2 os stop request. : can be used and interrupt r equest flag is cleared by ei 2 os interrupt clear signal. : cannot be used. : usable when an interrupt cause t hat shares the icr is not used. interrupt cause ei 2 os support interrupt vector interrupt control register priority number address icr address reset #08 08 h ffffdc h ?? high low int9 instruction #09 09 h ffffd8 h ?? exception processing #10 0a h ffffd4 h ?? a/d converter conversion termination #11 0b h ffffd0 h icr00 0000b0 h output compare ch0 match #12 0c h ffffcc h end of measurement by pwc timer ch0 / pwc timer ch0 overflow #13 0d h ffffc8 h icr01 0000b1 h 16-bit ppg timer ch0 #14 0e h ffffc4 h output compare ch1 match #15 0f h ffffc0 h icr02 0000b2 h 16-bit ppg timer ch1 #16 10 h ffffbc h output compare ch2 match #17 11 h ffffb8 h icr03 0000b3 h 16-bit reload timer ch1 underflow #18 12 h ffffb4 h output compare ch3 match #19 13 h ffffb0 h icr04 0000b4 h dtp/ext. interrupt ch0/ch1 detection #20 14 h ffffac h dtti output compare ch4 match #21 15 h ffffa8 h icr05 0000b5 h dtp/ext. interrupt ch2/ch3 detection #22 16 h ffffa4 h output compare ch5 match #23 17 h ffffa0 h icr06 0000b6 h end of measurement by pwc timer ch1 / pwc timer ch1 overflow #24 18 h ffff9c h dtp/ext. interrupt ch4 detection #25 19 h ffff98 h icr07 0000b7 h dtp/ext. interrupt ch5 detection #26 1a h ffff94 h dtp/ext. interrupt ch6 detection #27 1b h ffff90 h icr08 0000b8 h dtp/ext. interrupt ch7 detection #28 1c h ffff8c h waveform generator 16- bit timers ch0/ch1/ ch2 underflow #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer ch0 underflow #30 1e h ffff84 h 16-bit free-running timer zero detect #31 1f h ffff80 h icr10 0000ba h 16-bit ppg timer ch2 #32 20 h ffff7c h input capture ch0/ch1 #33 21 h ffff78 h icr11 0000bb h 16-bit free-running timer compare clear #34 22 h ffff74 h input capture ch2/ch3 #35 23 h ffff70 h icr12 0000bc h timebase timer #36 24 h ffff6c h uart ch1 receive #37 25 h ffff68 h icr13 0000bd h uart ch1 send #38 26 h ffff64 h uart ch0 receive #39 27 h ffff60 h icr14 0000be h uart ch0 send #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delayed interrupt generator module #42 2a h ffff54 h
mb90820 series 29 peripheral resources 1. low-power consumption control circuit the mb90820 series has the following cpu operating mode configured by se lection of an operating clock and clock operation control. clock mode pll clock mode : a pll clock that is a multiple of the oscillation clock (hclk) frequency is used to operate the cpu and peripheral functions. main clock mode : the main clock, with a frequency one- half that of the oscillation clock (hclk), is used to operate the cpu and peripheral functions. in main clock mode, the pll divide circuit is inactive. cpu intermittent operation mode cpu intermittent operation mode causes the cpu to o perate intermittently, while high-speed clock pulses are supplied to peripheral functions, r educing power consumption. in cpu intermittent operation mode, clock pulses are supplied intermittently to the cpu when it is accessing a register, internal memory, a peripheral function, or an external unit. standby mode in standby mode, the low power consumption contro l circuit reduces power consumption by stopping; ? the supply of the clock to cpu (sleep mode) ? cpu and peripheral functions (timebase timer mode) ? the oscillation clock itself (stop mode) pll sleep mode pll sleep mode is activated to stop the cpu operating cl ock when the microcontroller enters pll clock mode; other components continue to operate on the pll clock. main sleep mode main sleep mode is activated to stop the cpu operati ng clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. pll timebase timer mode pll timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, pll clock and timebase timer, to stop. all functi ons other than the timebase timer are deactivated. main timebase timer mode main timebase timer mode causes microc ontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. all functi ons other than the timeba se timer are deactivated. stop mode stop mode causes the source oscillati on to stop. all functions are deactivated.
mb90820 series 30 (1) register configuration 15 14 13 12 11 10 9 8 r/w 1 address: 00000a1 h r 1 r/w 1 r/w 1 r/w 1 r/w 10 r/w 0 clock selection register ckscr initial value read/write bit address: 0000a0 h 765432 10 low-power consumption mode control register lpmcr bit w 0 w 0 r/w 0 w 1 w 1 r/w 0 r/w 0 r/w 0 initial value read/write stp slp tmd cg1 cg0 reserved spl reserved mcm ws1 ws0 reserved cs1 cs0 rst mcs r/w 15 14 13 12 11 10 9 8 x address: 000002f h xxx w 0 w 00 w 0 pll clock control register pckcr initial value read/write bit reserved reserved cs2 reserved w ? ? ? ? ? ? ? ?
mb90820 series 31 (2) block diagram x0 3 x1 rst stp rst slp cg1 cg0 resv spl tmd reserved ws0 mcm mcs cs1 cs0 ws1 reserved 3 2 low power mode control register (lpmcr) pin pin pin divided by 2 divided by 512 divided by 2 divided by 4 divided by 2 pll multiplier circuit system clock generation circuit timebase timer stop signal release reset c ancel interruption cpu clock pin hi-z control clock selector clock selection register (ckscr) stop and sleep signals machine clock main clock oscillation stabilization waiting time is passed cpu clock control circuit pin high impedance control circuit internal reset generation circuit internal reset peripheral clock control circuit cpu intermittent operation selecter select intermittent cycles standby control circuit peripheral clock clock generator 2 3 4 6 divided by 2 cs2 pll clock control register (pckcr) 1 oscillation stabilization waiting time interval selecto r
mb90820 series 32 2. i/o ports (1) outline of i/o ports each i/o port outputs data from cpu to i/o pins or inputs signals from i/o pins to cpu through port data register (pdr). direction of the data flow (input or output) for each i/o pin can be designated in bit unit by port data direction register (ddr). the function of each port and the resource i/o multiplexed with it are described below: port 0 : general-purpose i/o port/resource (pwc timer) port 1 : general-purpose i/o port/resources (dtp / multi-functional timer) port 2 : general-purpose i/o port/resource (16-bit reload timer) port 3 : general-purpose i/o port/resource (16-bit ppg timer) port 4 : general-purpose i/o port/resources (16- bit ppg timer / 16-bit reload timer / uart / pwc) port 5 : general-purpose i/o port/resources (16-bit ppg timer / dtp) port 6 : general-purpose i/o port/resource (8/10-bit a/d converter) port 7 : general-purpose i/o port/resources (8/ 10-bit a/d converter / 8-bit d/a converter / uart/ 16-bit free-running timer / 16-bit input capture) port 8 : general-purpose i/o port/resources (1 6-bit input capture / multi-functional timer) (2) register configuration r/w: read/write enabled x : undefined register read/write address initial value port 0 data register (pdr0) r/w 000000 h xxxxxxxx b port 1 data register (pdr1) r/w 000001 h xxxxxxxx b port 2 data register (pdr2) r/w 000002 h xxxxxxxx b port 3 data register (pdr3) r/w 000003 h xxxxxxxx b port 4 data register (pdr4) r/w 000004 h xxxxxxxx b port 5 data register (pdr5) r/w 000005 h xxxxxxxx b port 6 data register (pdr6) r/w 000006 h xxxxxxxx b port 7 data register (pdr7) r/w 000007 h xxxxxxxx b port 8 data register (pdr8) r/w 000008 h xxxxxxxx b port 0 data direction register (ddr0) r/w 000010 h 00000000 b port 1 data direction register (ddr1) r/w 000011 h 00000000 b port 2 data direction register (ddr2) r/w 000012 h 00000000 b port 3 data direction register (ddr3) r/w 000013 h 00000000 b port 4 data direction register (ddr4) r/w 000014 h 00000000 b port 5 data direction register (ddr5) r/w 000015 h xxxxxx00 b port 6 data direction register (ddr6) r/w 000016 h 00000000 b port 7 data direction register (ddr7) r/w 000017 h 00000000 b port 8 data direction register (ddr8) r/w 000018 h 00000000 b a/d input enable regi ster (ader0) r/w 0000c5 h 11111111 b a/d input enable regi ster (ader1) r/w 0000d0 h 11111111 b port 0 pull-up resistor setting register (rdr0) r/w 00008c h 00000000 b port 1 pull-up resistor setting register (rdr1) r/w 00008d h 00000000 b port 2 pull-up resistor sett ing register (rdr2) r/w 00008e h 00000000 b port 3 pull-up resistor setting register (rdr3) r/w 00008f h 00000000 b
mb90820 series 33 (3) block diagram block diagram of port 0 (p00 to p06), po rt 1 (p17) and port 2 (excluding p21) pins block diagram of port 0 (p07) and port 2 (p21) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin rdr pull-up resistor resource input standby control (spl=1) standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable rdr pull-up resistor resource input standby control (spl=1) standby control (spl=1)
mb90820 series 34 block diagram of port 1 (p10 to p16) pins block diagram of port 3 (excluding p37) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin rdr pull-up resist or resource input external interrupt enable standby control (spl=1) standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin rdr pull-up resist or standby control (spl=1) standby control (spl=1)
mb90820 series 35 block diagram of port 3 (p37) pin block diagram of port 4 pins (excluding p41, p45 and p46) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable rdr pull-up resist or standby control (spl=1) standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable resource input standby control (spl=1)
mb90820 series 36 block diagram of port 4 (p41 and p46) pins block diagram of p45 pin internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource input standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl=1) level selection bit uart ch0 data input uart ch0 data input
mb90820 series 37 block diagram of port 5 (p50) pin block diagram of port 5 (p51) pin internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable resource input standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource input externa l interrup t enable standby control (spl=1)
mb90820 series 38 block diagram of port 6 pins block diagram of port 7 (p70 and p71) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin ader a/d converter input a/d converter channel selection bit standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin ader a/d converter input d/a converter output a/d converter channel selection bit d/a converter output enable bit standby control (spl=1)
mb90820 series 39 block diagram of p72 pin block diagram of port 7(p73 and p74) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin ader a/d converter input a/d converter channel selection bit level selection bit uart ch1 data input uart ch1 data input standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable ader resource input a/d converter input a/d converter channel selection bit standby control (spl=1)
mb90820 series 40 block diagram of port 7 (p75 to p77) pins block diagram of port 8 (p80 and p81) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin ader resource input a/d converter input a/d converter channel selection bit standby control (spl=1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource input standby control (spl=1)
mb90820 series 41 block diagram of port 8 (p82 to p87) pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin resource output resource output enable resource input standby control (spl=1)
mb90820 series 42 3. timebase timer the timebase timer is an 18-bit free-running counter (t imebase counter) that counts up in synchronization with the internal count clock (divided by 1/2 of oscillation clock). features of timebase timer : generates the interruption at counter-overflow supports for ei 2 os interval timer function: generates an interrupt at four different time intervals clock supply function: four different clock can be selected as watchdog timer?s count clock supply clock for oscillation stabilization (1) register configuration (2) block diagram 15 14 13 12 11 10 9 8 r/w 1 address: 0000a9 h r/w 0 r/w 0 w 1 r/w 0 r/w 0 reserved tbie tbof tbr tbc1 tbc0 timebase timer control register tbtc initial value read/write bit number xx ? ? ? ? of: overflow hclk: oscillation clock *1: switching of the machine clock from the oscillation clock to the pll clock *2: interrupt number of of of timebase timer counter divided by 2 of hclk power-on reset stop mode start counter clear circuit interval timer selector to watchdog timer to the oscillation setting time selector in the clock control section 2 1 2 2 2 3 . . . . . . 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 ? ? ? of counter clear reserved ? tbr tbc1 tbc0 ? tbie tbof ckscr: mcs = 1, 0* 1 timebase timer control register (tbtc) tbof clear tbof set timebase timer interrupt signal #36 (24 h )* 2
mb90820 series 43 4. watchdog timer the watchdog timer is a 2-bit counter that uses the ti mebase timer?s supply clock as the count clock. after activation, if the watchdog timer is not cleare d within a given period, the cpu will be reset. features of watchdog timer : reset cpu at four different time intervals indicate the reset causes by status bits (1) register configuration (2) block diagram address: 0000a8 h 76543210 watchdog timer control register wdtc bit r x r x r x r x w 1 w 1 w 1 initial value read/write ponr wrst erst srst wte wt1 wt0 x ? ? watchdog timer control register (wdtc) ponr wrst erst srst wte wt1 wt0 watchdog timer 2 start of sleep mode start of hold status mode start of stop mode counter clear control circuit count clock selector 2-bit counter watchdog reset generator activation with clr over flow clr clr clear to the internal reset generato r timebase timer counter divided by 1/2 of hclk hclk : oscillation clock frequency 4 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18
mb90820 series 44 5. 16-bit reload timer ( 2) the 16-bit reload timer provides two operating mode, internal clock mode and event count mode. in each operating mode, the 16-bit down counter can be reloaded (reload mode ) or stopped by underflow (one-shot mode). output pins to1 and to0 are able to output different waveform according to the counter operating mode. to1 and to0 toggles when counter underflows if counter is operated as reload mode. to 1 and to0 output specified level (h or l) during counting if the counter is in one-shot mode. features of the 16-bit reload timer : interrupt when timer underflows supports for ei 2 os internal clock operating mode : three internal count clocks can be selected. counter can be activated by software or extern al trigger (signal at tin1 and tin0 pins). counter can be reloaded or stopp ed when underflow after activated. event count operating mode : counter counts down one by one with s pecified edge at tin1 and tin0 pins. counter can be reloaded or stopped when underflow. (1) register configuration note : registers tmr0, tmr1/tmrd0, tmrd1 are word access only. 15 14 13 12 11 10 9 8 bit 16-bit timer register (upper)/16-b it reload timer register (upper) 7 6 5 4 3 2 1 0 bit 16-bit timer register (lower)/16-b it reload timer register (lower) address: ch0 000085 h ch1 000089 h tmr0 , tmr1 / r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write address: ch0 000084 h ch1 000088 h initial value read/write tmr0 , tmr1 / d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x tmrd0 , tmrd1 tmrd0 , tmrd1 15 14 13 12 11 10 9 8 bit timer control status register (upper) 7 6 5 4 3 2 1 0 bit timer control status register (lower) address: ch0 000083 h ch1 000087 h tmcsrh0 , r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write address: ch0 000082 h ch1 000086 h initial value read/write tmcsrl0 , csl1 csl0 mod2 mod1 mod0 oute outl reld inte uf cnte trg r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 fsel r/w 1 xx x tmcsrh1 tmcsrl1 ? ? ? ? ? ?
mb90820 series 45 (2) block diagram timer control status register (tmcsr0) * 1 prescaler _ _ csl1 csl0 mod2 mod1 _ outl oute reld inte uf cnte trg mod0 internal data bus input control circuit clock selector clock judgement circuit 16-bit reload register 16-bit timer register (down-counter) uf machine clock interrupt request signal #30 * 2 <#18> pin pin reload control circuit output signal generation circuit operation control circuit tmr0 * 1 tmrd0 * 1 reload signal wait signal to uart ch0, ch1 * 1 p42/to0 * 1 en p41/tin0 * 1 select signal rever- sed external clock function select output control circuit gate input internal clock clear 2 3 3 clk clk *1: used for ch0/1. <> indicates ch1. *2: interrupt number fsel 1-bit down-counter clock selector 1 0 fsel: initial value "1" count clock generation circuit
mb90820 series 46 6. 16-bit ppg timer ( 3) the 16-bit ppg timer consists of a 16-bit down counter , prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a ppg output pin. this module can be used to output pulses syn- chronized by software trigger or gate signal from mult i-functional timer, refer to ?7. multi-functional timer?. features of 16-bit ppg timer : two operating mode : pwm and one-shot mode 8 types of counter operation clock ( , /2, /4, /8, /16, /32, /64, /128) can be selected interrupt is generated when trigger signal or co unter borrow occurs, or when ppg output is changed supports for ei 2 os (1) register configuration (continued) 15 14 13 12 11 10 9 8 bit ppg period setting register (upper) address: ch0 00003b h ch1 000043 h ch2 00004b h pcsr0 to w x w x w x w x w x w x w x w x initial value read/write cs15 cs14 cs13 cs12 cs11 cs10 cs09 cs08 76543210 bit ppg control status register (lower) 15 14 13 12 11 10 9 8 bit ppg control status register (upper) address: ch0 00003e h ch1 000046 h ch2 00004e h pcntl0 to r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write pcnth0 to address: ch0 00003f h ch1 000047 h ch2 00004f h cnte stgr mdse rtrg cks1 cks0 pgms cks2 iren irqf irs1 irs0 poen osel 15 14 13 12 11 10 9 8 ppg duty setting register (upper) 7 6 5 4 3 2 1 0 bit ppg duty setting register (lower) address: ch0 00003d h ch1 000045 h ch2 00004d h pdut0 to w x w x w x w x w x w x w x w x initial value read/write address: ch0 00003c h ch1 000044 h ch2 00004c h w x w x w x w x w x w x w x w x initial value read/write pdut0 to du15 du14 du13 du12 du11 du10 du09 du08 du07 du06 du05 du04 du03 du02 du01 du00 bit xx pcnth2 pcntl2 pdut2 pdut2 pcsr2 ? ? ? ?
mb90820 series 47 (continued) note : registers pdcr0 to pdcr2, pcsr0 to pc sr2 and pdut0 to pdut2 are word access only. 15 14 13 12 11 10 9 8 bit ppg down counter register (upper) 7 6 5 4 3 2 1 0 bit ppg down counter register (lower) address: ch0 000039 h ch1 000041 h ch2 000049 h pdcr0 to r 1 r 1 r 1 r 1 r 1 r 1 r 1 r 1 initial value read/write address: ch0 000038 h ch1 000040 h ch2 000048 h r 1 r 1 r 1 r 1 r 1 r 1 r 1 r 1 initial value read/write pdcr0 to dc15 dc14 dc13 dc12 dc11 dc10 dc09 dc08 dc07 dc06 dc05 dc04 dc03 dc02 dc01 dc00 7 6 5 4 3 2 1 0 bit ppg period setting register (lower) address: ch0 00003a h ch1 000042 h ch2 00004a h w x w x w x w x w x w x w x w x initial value read/write pcsr0 to cs07 cs06 cs05 cs04 cs03 cs02 cs01 cs00 pdcr2 pcsr2 pdcr2
mb90820 series 48 (2) block diagram 1/1 1/2 1/4 1/8 1/16 1/32 1/64 period setting register 0/1/2 clk load start borrow 16-bit down counter comparator s q r interrupt selection prescaler machine clock mdse pgms osel poen ppg0 (multi-functional timer) or ppg1 (multi-pulse generator) or ppg2 pin p37/ppg0 or p40/ppg1 or p50/ppg2 interrupt irs1 irs0 irqf iren down counter register 0/1/2 cks2 cks1 cks0 f 2 mc-16lx bus 1/128 stop edge detection stgr cnte rtrg #14, #16, #32 gate - from multi-functional timer (for ppg0 only) (for ppg1 & ppg2) period setting buffer register 0/1/2 duty setting buffer register 0/1/2 duty setting register 0/1/2
mb90820 series 49 7. multi-functional timer the 16-bit multi-functional timer module consists of one 16- bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit ppg timer. this modu le allows six independent waveforms generated by ppg timer or waveform generator to be ou tputted. with the 16-bit free-running timer and the input capture circuit, input pulse width and exte rnal clock period measurement can be done. (1) 16-bit free-running timer (1 channel) the 16-bit free-running timer cons ists of a 16-bit up counter, 16-bit up-down counter, timer control status register, 16-bit compare clear register (with buffer register) and a prescaler. 8 types of counter operation clock ( , /2, /4, /8, /16, /32, /64, /128) can be selected. ( is the machine clock.) two types of interrupt causes : - compare clear interrupt is generated when there is a comparing match with compare clear register and 16- bit free-running timer. - zero detection interrupt is generated while 16-bit fr ee-running timer is detected as zero in count value. ei 2 os supported. compare-clear register buffer provided : the selectable buffer enables the 16-bit free-running timer update its compare-clear register automatically without stop the timer operation. user can read the next compare-clear value to the compare-clear register when the timer is running. the compare-clear re gister will be updated when the timer value is ?0000 h ? reset, software clear, compare match with compare cl ear register in up-count mode will reset the counter value to ?0000 h ?. supply clock to output compare module : the prescaler output is acted as the count clock of the output compare. (2) output compare module ( 6 channels) the output compare module consists of six 16-bit output compare register s (with selectable buffer register), compare output latch and compare control registers. an interrupt is generated and output level is inverted when the value of 16-bit free-running timer and output compare register are matched. 6 output compare registers can be operated independently. output pins and interrupt flag are corres ponding to each output compare register. 2 output compare registers can be paired to control the output pins. inverts output pins by using 2 output compare registers together. setting the initial value for each output pin is possible. interrupt is generated when there is a comparing matc h with output compare register and 16-bit free-running timer. ei 2 os supported. (3) input capture module (4 channels) input capture consists of 4 independent external input pins, the corresponding input capture data register and input capture control status register. by detecting any edge of the input signal from the external pin, the value of the 16-bit free-running timer can be stored in the capt ure register and an interrupt is generated simultaneously. operations synchronized with the 16-bi t free-running timer?s count clock. 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show t he trigger edge is rising or falling. 4 input captures can be operated independently. two independent interrupts are generated when detecting a va lid edge from external input. ei 2 os supported.
mb90820 series 50 (4) 16-bit ppg timer (1 channel) the 16-bit ppg timer 0 is used to provide a ppg signa l for waveform generator. (see section ?6. 16-bit ppg timer ( 3) ?.) (5) waveform generator module the waveform generator consists of three 16-bit timer regi sters, three 16-bit timer control registers and a wave- form control register. with waveform generator, it is possible to generate real time output, 16-bit ppg waveform output, non-overlap 3-phase waveform output for inverter c ontrol and dc chopper waveform output. it is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (dead-time timer function) it is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (dead-time timer function) by detecting realtime output compare match, gate signal of the ppg timer operation will be generated to start or stop ppg timer operation. (gate function) when a match is detected by real ti me output compare, the 16-bit timer is activated. the ppg timer can be started or stopped easily by generating a gate signal for ppg operation until the 16-bit timer stops. (gate function) force to stop output waveform using dtti pin input. interrupt is generated when dtti active or 16-bit timer underflow. ei 2 os is supported. (6) register configuration 16-bit free-running timer registers (continued) 15 14 13 12 11 10 9 8 r/w 0 address: 00005d h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 address: 00005c h 76543210 timer data register (upper) timer data register (lower) tcdt tcdt initial value read/write bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit t07 t06 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 r/w 0 address: 00005f h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 msi2 msi1 msi0 iclr icre timer control status register (upper) initial value read/write bit tccsh ecke irqzf irqze address: 00005e h 76 543210 timer control status register (lower) tccsl bit r/w 0 r/w 1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bfe stop mode sclr clk2 clk1 clk0 x ? ?
mb90820 series 51 (continued) note : registers tcdt, cpclrb/cpclr are word access only. output compare registers note : register occpb0 to occpb5 and occp0 to occp5 are word access only. address: 00005a h 76543210 compare clear buffer register / compare clear register (lower) cpclrb/cpclr bit r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 initial value read/write cl07 cl06 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 r/w 1 address: 00005b h r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 cl15 cl14 cl13 cl12 cl11 cl10 cl09 cl08 compare clear buffer register / compare clear register (upper) cpclrb/cpclr initial value read/write bit 15 14 13 12 11 10 9 8 bit output compare buffer register / output compare register (upper) 7 6 5 4 3 2 1 0 bit output compare buffer register / output compare register (lower) address: ch0 000071 h ch1 000073 h ch2 000075 h ch3 000077 h ch4 000079 h ch5 00007b h occpb0 to r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write op15 op14 op13 op12 op11 op10 op09 op08 address: ch0 000070 h ch1 000072 h ch2 000074 h ch3 000076 h ch4 000078 h ch5 00007a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write occpb0 to op07 op06 op05 op04 op03 op02 op01 op00 15 14 13 12 11 10 9 8 bit compare control register (upper) 7 6 5 4 3 2 1 0 bit compare control register (lower) address: ch1 00007d h ch3 00007f h ch5 000081 h ocs1/3/5 r/w 1 r/w 1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write cmod ote1 ote0 otd1 otd0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 1 r/w 1 r/w 0 r/w 0 initial value read/write ocs0/2/4 iop1 iop0 ioe1 ioe0 cst1 cst0 address: ch0 00007c h ch2 00007e h ch4 000080 h buf0 buf1 bts1 bts0 occp0 to occp0 to x occpb5/ occp5 occpb5/ occp5 ? ?
mb90820 series 52 input capture registers note : registers ipcp0 to ipcp3 are word access only. 15 14 13 12 11 10 9 8 bit input capture data register (upper) address: ch0 000061 h ch1 000063 h ch2 000065 h ch3 000067 h ipcp0 to xxxxxx x x initial value read/write cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 r r r r r r r r 7 6 5 4 3 2 1 0 bit input capture data register (lower) address: ch0 000060 h ch1 000062 h ch2 000064 h ch3 000066 h xx xx xx x x initial value read/write ipcp0 to cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 r r r r r r r r 15 14 13 12 11 10 9 8 address: 00006b h r 0 r 0 iei3 iei2 input capture control stat us register (2/3) (upper) icsh23 initial value read/write bit 765 4 3 2 10 r/w 0 address: 00006a h r/w 0 r/w 0 r/w 0 r/w r/w 0 r/w 0 r/w 0 icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 input capture control status register (2/3) (lower) icsl23 initial value read/write bit 0 address: 000068 h 76543210 input capture control status register (0/1) (lower) bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 picsl01 address: 000069 h 15 14 13 12 11 10 9 8 ppg output control/ input capture cont rol status register (0/1) (upper) bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r 0 r 0 initial value read/write iei1 iei0 picsh01 pgen0 pgen1 pgen2 pgen3 pgen4 pgen5 x x x x x x ipcp3 ipcp3 ? ? ? ? ? ? ? ? ? ? ? ?
mb90820 series 53 waveform generator registers note : registers tmrr0 to tmrr2 are word access only. 765432 1 0 bit 16-bit timer control register 15 14 13 12 11 10 9 8 bit 16-bit timer register (upper) address: ch0 000056 h ch2 000058 h dtcr0, dtcr2 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write tmrr0 to address: ch0 000051 h ch1 000053 h ch2 000055 h dmod gten1 gten0 tmif tmie tmd2 tmd1 tmd0 address: 000059 h 15 14 13 12 11 10 9 8 waveform control register sigcr bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write dtie dtif nrsl dck2 dck1 dck0 nws1 nws0 7 6 5 4 3 2 1 0 bit 16-bit timer register (lower) r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write tmrr0 to address: ch0 000050 h ch1 000052 h ch2 000054 h 15 14 13 12 11 10 9 8 bit 16-bit timer control register address: ch1 000057 h dtcr1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write dmod gten1 gten0 tmif tmie tmd2 tmd1 tmd0 tr15 tr14 tr13 tr12 tr11 tr10 tr09 tr08 tr07 tr06 tr05 tr04 tr03 tr02 tr01 tr00 tmrr2 tmrr2
mb90820 series 54 ? mcu to 3-phase motor interface circuit rto0 (u) , rto2 (v) , rto4 (w) are called ?upper arm?. rto1 (x) , rto3 (y) , rto5 (z) are called ?lower arm?. rto0 (u) and rto1 (x) are called ?non-overlapping output pair?. rto2 (v) and rto3 (y) are call ed ?non-overlapping output pair?. rto4 (w) and rto5 (z) are called ?non-overlapping output pair?. (u) , (v) , (w) are t he 3-phase coil connection. ? 3-phase motor coil connection circuit rto4(w) (v) rto5(z) (w) rto2(v) (u) rto3(y) rto0(u) rto1(x) v cc (u) (v) (w) (v) (w) (u) star connection circuit delta connection circuit
mb90820 series 55 (7) block diagram block diagram of multi-functional timer interrupt #12 output compare 0 interrupt #31 zero detect interrupt #15 output compare 1 i nterrupt #34 compare clear interrupt #17 output compare 2 int errupt #33 input compare 0/1 interrupt #19 output compare 3 int errupt #35 input compare 2/3 interrupt #21 output compare 4 interrupt #23 output compare 5 f 2 mc-16lx bus 16-bit output compare 16-bit free-running timer 16-bit input capture buffer transfer interrupt #12 interrupt #15 interrupt #17 interrupt #19 interrupt #21 interrupt #23 rt0 to rt5 output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5 waveform generator rto0 rto1 rto2 rto3 rto4 rto5 dtti interrupt #29 interrupt #31 interrupt #34 a/d trigger exck interrupt #33 interrupt #35 in0 in1 in2 in3 pin p82/rto0 (u) pin p83/rto1 (x) pin p84/rto2 (v) pin p85/rto3 (y) pin p86/rto4 (w) pin p87/rto5 (z) pin p10/int0/dtti 16-bit timer 0/1/2 underflow rt0 to 5 pin p75/frck/an13 pin p76/in0/an14 pin p77/in1/an15 pin p80/in2 pin p81/in3 input capture 0/1 input capture 2/3 zero detect compare clear a/d trigger real time i/o ppg0 gate ppg0 gate interrupt #20 dtti falling edge detect counter value counter value
mb90820 series 56 block diagram of 16-bit free-running timer stop mode sclr clk2 clk1 clk0 clr ck i0 i1 o i0 i1 i0 i1 o o i0 i1 o msi2 msi1 msi0 iclr icre irqzf irqze prescaler zero detect circuit compare circuit 16-bit free-running timer 16-bit compare clear register 16-bit compare clear buffer register mask circuit selector selector selector selector f 2 mc-16lx bus interrupt #34 (22 h ) interrupt #31 (1f h ) a/d trigger compare clear match to output compare to input compare & output compare zero detect (to output compare) stop up/ up-down transfer
mb90820 series 57 block diagram of 16-bit output compare block diagram of 16-bit input capture output compare register 0/2/4 compare circuit t q output compare register 1/3/5 compare circuit t q rt0/2/4 cmod rt1/3/5 iop1 iop0 ioe1 ioe0 interrupt #12, #17, #21 #15, #19, #23 generator) generator) count value from free-running timer (waveform (waveform output compare buffer buf0 bts0 zero detect from compare clear match from free-running timer f 2 mc-16lx bus selector i0 i1 o transfer output compare buffer transfer buf1 bts1 selector i0 i1 o free-running timer register 0/2/4 register 1/3/5 eg11 eg10 eg01 eg00 iei1 iei0 icp0 icp1 ice0 ice1 in0/2 edge detect input capture data register 1/3 in1/3 edge detect interrupt #33, #35 #33, #35 count value from free-running timer f 2 mc-16lx bus input capture data register 0/2
mb90820 series 58 block diagram of waveform generator f 2 mc-16lx bus divider dck2 dck1 dck0 nrsl dtif dtie 16-bit timer 0 compare circuit 16-bit timer register 0 16-bit timer 1 compare circuit 16-bit timer register 1 16-bit timer 2 compare circuit 16-bit timer register 2 dtti control circuit selector dead time generator waveform control selector dead time generator waveform control selector dead time generator waveform control selector selector selector sigcr dtcr2 dtcr1 tmd2 tmd1 tmd0 gten1 gten0 dtcr0 tmd2 tmd1 tmd0 gten1 gten0 tmd2 tmd1 tmd0 gten1 gten0 output control output control output control rto0 (u) rto1 (x) rto2 (v) rto3 (y) rto4 (w) rto5 (z) pgen1 pgen0 picsh01 rt0 rt1 rt2 rt3 rt4 rt5 z w to5 to4 y v to3 to2 x u to1 to0 gate 0/1 gate 2/3 gate 4/5 gate ppg0 dtti pgen3 pgen2 picsh01 pgen5 pgen4 picsh01 (to ppg0 ) nws1 nws0 noise cancellation
mb90820 series 59 8. pwc timer ( 2) the pwc (pulse width count) timer is a 16-bit multi-fu nctional up counter with reload timer functions and input signal pulse width count functions. the pwc timer consists of a 16-bit counter, an input pul se divider, a division ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. the pwc timer has the following features: interruption is generated when timer overflow or end of pwc measurement. ei 2 os is supported. timer functions : - generates an interrupt reque st at set time intervals. - outputs pulse signals synchronized with the timer cycle. - selects the counter clock from three internal clocks. pulse-width count functions: - counts the time between external pulse input events. - selects the counter clock from three internal clocks. - count mode: ? h pulse width (rising edge to falling edge) / l pulse width (falling edge to rising edge) ? rising-edge cycle (rising edge to falling edge) / falling-edge cycle (falling edge to rising edge) ? count between edges (rising or fa lling edge to falling or rising edge) capable of counting cycles by dividing input pulses by 2 2 , 2 4 , 2 6 , 2 8 using an 8-bit input divider. generates an interrupt request upon the completion of count operation. selects single or consecutive count operation. (1) register configuration note : registers pwc0, pwc1 are word access only. (continued) 7 6 5 4 3 2 1 0 bit division ratio control register r/w 0 r/w 0 initial value read/write div0, div1 address: ch0 0000c4 h ch1 00002c h div1 div0 15 14 13 12 11 10 9 8 bit pwc data buffer register (upper) r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write pwc0, pwc1 address: ch0 0000c3 h ch1 00002b h 7 6 5 4 3 2 1 0 bit pwc data buffer register (lower) r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write pwc0, pwc1 address: ch0 0000c2 h ch1 00002a h pw15 pw14 pw13 pw12 pw11 pw10 pw09 pw08 pw07 pw06 pw05 pw04 pw03 pw02 pw01 pw00 x x x x x x ? ? ? ? ? ? ? ? ? ? ? ?
mb90820 series 60 (continued) note : registers pwc0, pwc1 are word access only. (2) block diagram 15 14 13 12 11 10 9 8 bit pwc control status register (upper) r/w 0 r/w 0 r 0 r/w 0 r/w 0 r/w 0 r/w 0 r 0 initial value read/write pwcsh0, address: ch0 0000c1 h ch1 000029 h 7 6 5 4 3 2 1 0 bit pwc control status register (lower) r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write pwcsl0, address: ch0 0000c0 h ch1 000028 h strt stop edir edie ovir ovie err pout cks1 cks0 reserved reserved s/c mod2 mod1 mod0 pwcsh1 pwcsl1 f 2 mc-16lx bus pwc clock error detection err 16-bit up counter control circuit pwcs reload data transfer pwc read 16 16 write enabled 16 16 overflow clock divider clock 2 2 2 3 internal clock (machine clock / 4) edge detection 2 division ratio selection err cks1, cks0 start edge selection count end edge end edge selection divider on/off count bit output flag setting count start edge count end interrupt request overflow interrupt request 8-bit divider divr overflow f.f. timer clear count enabled cks1, cks0 divider clear 15 p06/pwi0, p07/pwo0, p46/pwi1 p47/pwo1
mb90820 series 61 9. uart ( 2) the uart is a serial i/o port for asynchronous (sta rt-stop) communication or clock-synchronous communication. the uart has the following features : full-duplex double buffering capable of asynchronous (start-stop bit) and clk-synchronous communications support for the multiprocessor mode various method of baud rate generation : - external clock input possible - internal clock (a clock supplied fr om 16-bit reload timer can be used.) - embedded dedicated ba ud rate generator note : assuming internal machine clock frequencies of 6 mhz, 8 mhz, 10 mh z, 12 mhz, and 16 mhz. error detection functions (parity, framing, overrun) nrz (non return to zero) signal format interrupt request : - receive interrupt (receive comp lete, receive error detection) - transmit interrupt (transmission complete) - transmit / receive conforms to extended intelligent i/o service (ei 2 os). operation baud rate asynchronous 31250/9615/4808/2404/1202 bps clk synchronous 2 m/1 m/500 k/250 k/125 k/62.5k bps
mb90820 series 62 (1) register configuration 15 14 13 12 11 10 9 8 bit serial status register r 0 r 0 r 0 r 0 r 1 r/w 0 r/w 0 r/w 0 initial value read/write ssr0, ssr1 address: ch0 000023 h ch1 000027 h 7 6 5 4 3 2 1 0 bit serial input data register / serial output data register r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write sidr0, sidr1/ address: ch0 000022 h ch1 000026 h pe ore fre rdrf tdre bds rie tie sodr0, sodr1 15 14 13 12 11 10 9 8 bit serial control register r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 1 r/w 0 r/w 0 initial value read/write scr0, scr1 address: ch0 000021 h ch1 000025 h 7 6 5 4 3 2 1 0 bit serial mode register r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write smr0, smr1 address: ch0 000020 h ch1 000024 h pen p sbl cl a/d rec rxe txe mod1 mod0 cs2 cs1 cs0 rst scke soe 15 14 13 12 11 10 9 8 bit clock division control register r/w 0 r/w 0 r/w 0 initial value read/write cdcr0, address: ch0 000035 h ch1 000037 h md div2 div1 div0 d0 d1 d2 d3 d4 d5 d6 d7 r/w 0 ils r/w 0 xx x cdcr1 ? ? ? ? ? ?
mb90820 series 63 (2) block diagram f 2 mc-16lx bus md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sidr0/1 sodr0/1 p44/sot0 p45/sin0 baud rate external clock clock reception clock transmission clock reception interrupt transmission reception control generator selector interrupt reception bit circuit counter reception parity counter transmission control transmission transmission bit transmission reception state reception error shift register circuit start circuit counter parity counter judgment circuit start of transmission smr0/1 scr0/1 ssr0/1 control signal register register register start bit detection circuit end of reception from communication prescaler 16-bit reload timer control bus p43/sck0 #39 (27 h )* <#37 (25 h )*> #40 (28 h )* <#38 (26 h )*> *: interrupt number bds rst shift register for transmission for reception generating circuit for ei 2 os
mb90820 series 64 10. dtp/external interrupts the dtp/external interrupt circuit is activated by the si gnal supplied to a dtp/external interrupt pin. the cpu accepts the signal using the same procedure it uses for normal hardw are interrupts and generates external interrupts or activates the extended intelligent i/o service (ei 2 os). features of dtp/external interrupt : total 8 external interrupt channels. two request levels (?h? and ?l?) are prov ided for the intelligent i/o service. four request levels (rising edge, falling edge, ?h? level and ?l? level) are provided for external interrupt requests. (1) register configuration 15 14 13 12 11 10 9 8 r/w 0 address: 0000031 h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 dtp/interrupt source register eirr initial value read/write bit address: 000030 h 76543210 dtp/interrupt enable register enir bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write en7 en6 en3 en2 en1 en0 en5 er7 er6 er5 er4 er3 er2 er1 er0 en4 15 14 13 12 11 10 9 8 r/w 0 address: 0000033 h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 request level setting register (upper) elvrh initial value read/write bit address: 000032 h 76543210 request level setting register (lower) elvrl bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write lb3 la3 lb1 la1 lb0 la0 lb2 lb7 la7 lb6 la6 lb5 la5 lb4 la4 la2
mb90820 series 65 (2) block diagram request level setting register (elvr) p10/int0/dt ti pin p11/int1 pin p12/int2 pin p13/int3 pin p14/int4 pin p15/int5 pin lb7 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p16/int6 pin p51/int7 pin selector selector selector selector selector selector selector selector er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 interrupt request numb er #20(14 h ) #22(16 h ) #25(19 h ) #27(1b h ) internal data bus 22 2 2 2 2 2 2 #26(1a h ) #28(1c h )
mb90820 series 66 11. delayed interrupt generation module the delayed interrupt generation module is used to generat e a task switching interrupt. interrupt requests to the f 2 mc-16lx cpu can be generated and cleared by software using this module. (1) register configuration (2) block diagram 15 14 13 12 11 10 9 8 address: 00009f h r/w r0 delay interrupt cause/clear register dirr initial value read/write bit 0 x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? f 2 mc-16lx bus delayed interrupt cause gener ating/cancellation decoder interrupt cause latch
mb90820 series 67 12. a/d converter the a/d converter converts the analog voltage input (input voltage) to an analog input pin to a digital value. it has the following features : the minimum conversion time is 3 s (for a ma chine clock of 24 mhz; including sampling time). the converter uses the rc-type succ essive approximation conversion method with a sample and hold circuit. a resolution of 10 bits or 8 bits can be set. up to 16 channels for analog input pins can be selected by a program. various conversion mode : - single conversion mode : selectively convert one channel. - scan conversion mode : continuously convert mult iple channels. maximum of 16 selectable channels. - continuous conversion mode : repea tedly convert specified channels. - stop conversion mode : convert one channel then halt until the next activation (enables synchronization of the conversion start timing). at the end of a/d conversion, an interrupt reque st can be generated and ei2os can be activated. in the interrupt-enabled state, the conversion data prot ection function prevents any part of the data from being lost through continuous conversion. the conversion can be activated by software, 16-bit re load timer 1 (rising edge) and 16-bit free-running timer zero detection edge. (1) register configuration (continued) 15 14 13 12 11 10 9 8 r/w 0 address: 00000c7 h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 0 a/d control status register 1 (upper) adcs1 initial value read/write bit address: 0000c6 h 765432 10 a/d control status register 0 (lower) adcs0 bit r/w 0 r/w 0 r/w 00 initial value read/write md1 md0 s10 busy int inte paus sts1 sts0 strt reserved 15 14 13 12 11 10 9 8 address: 00000c9 h r x r x a/d data register 1 (upper) adcr1 initial value read/write bit address: 0000c8 h 76 54 3 2 10 a/d data register 0 (lower) adcr0 bit r x r x r x r x r x r x r x r x initial value read/write d7 d6 d3 d2 d1 d0 d5 d9 d8 d4 x x x x x x x x x x x ? ? ?? ???? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
mb90820 series 68 (continued) 15 14 13 12 11 10 9 8 r/w 0 address: 00000cb h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 a/d setting register 1 (upper) adsr1 initial value read/write bit address: 0000ca h 765432 10 a/d setting register 0 (lower) adsr0 bit r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 00 r/w 0 initial value read/write ans2 ans1 ane3 ane2 ane1 ans0 st2 st1 st0 ct2 ct1 ct0 reserved reserved 15 14 13 12 11 10 9 8 address: 00000c5 h a/d input enable register 0 ader0 initial value read/write bit address: 0000d0 h 76 54 3 2 10 a/d input enable register 1 ader1 bit initial value read/write ade15 ade14 ade11 ade10 ade9 ade8 ade13 ade7 ade6 ade5 ade4 ade3 ade1 ade0 ade12 ans3 r/w 0 r/w ane0 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 11 r/w 1 r/w r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 11 r/w 1 r/w ade2
mb90820 series 69 (2) block diagram f 2 mc-16lx bus av cc avr av ss d/a converter sequential compare register data register adcr0/1 comparator sample and hold circuit mpx port 6 port 7 input circuit input circuit an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 decorder a/d setting register 0 a/d setting register 1 adsr0/1 prescaler operation clock a/d control status register 0 a/d control status register 1 a/d input enable register 0 a/d input enable register 1 ader0/1 adcs0/1 16-bit reload timer 1 1 6-bit free-running timer zero detection : machine clock
mb90820 series 70 13. d/a converter the d/a converter is used to generate an analog output from an 8-bit digital input. by setting the enable bit in the d/a control register (dacr) to 1, it will enable the corresponding d/a out put channel. hence, setting this bit to 0 will disable that channel. if d/a output is disabled, the analog switch inserted to the output of each d/a co nverter channel in series is turned off. in the d/a converter, the bi t is cleared to 0 and the direct-current path is shut off. the above is also true in the stop mode. the output voltage of the d/a converter ranges from 0 v to 255/256 av cc . to change the output voltage range, adjust the av cc voltage externally. the d/a converter output does not have the internal buffer amplifier. the analog switch (= 100 ?) is inserted to the output in series. to apply load to the output ex ternally, estimate a sufficient stabilization time. table below lists the theoretical values of output voltage of the d/a converter. value written to da07 to da00 and da17 to da10 theoretical value of output voltage 00 h 0/256 av cc (= 0 v) 01 h 1/256 av cc 02 h 2/256 av cc :: fd h 253/256 av cc fe h 254/256 av cc ff h 255/256 av cc
mb90820 series 71 (1) register configuration da17 da16 da15 da14 da13 da12 da11 da10 dat1 15 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x da07 da06 da05 da04 da03 da02 da01 da00 dat0 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 14 13 8 10 9 7 6 43 0 d /a data register 1 address:0000cd h read/write initial value d /a data register 0 address:0000cc h read/write initial value d /a control register 1 address:0000cf h read/write initial value d /a control register 0 address:0000ce h read/write initial value dae1 dacr 1 - x - x - x - x - x - x - x r/w 0 dae0 dacr 0 - x - x - x - x - x - x - x r/w 0 - - - - - 15 14 13 8 10 9 - - - - - - 7 6 4 3 0 bit bit bit bit 11 12 51 2 11 12 - - - 5 1 2
mb90820 series 72 (2) block diagram 2 mc-16lx bus da da da da da da da da da da da da da da da da 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 av cc av cc da17 da07 2r 2r r r da16 da06 2r 2r r r da15 da05 da11 da01 2r 2r r r da10 da00 2r 2r 2r 2r dae1 standby control dae0 standby control da output ch1 da output ch0 f
mb90820 series 73 14. rom correction function when the corresponding address matches the value set in the address detect ion register, the instruction code to be loaded into the cpu is forced to be re placed with the int9 instruction code (01 h ). when executing a set instruction, the cpu executes the int9 instruction. t he address detection function is implemented by processing using the int9 instruction routine. the device contains two address detection registers, each provided with a compare enable bit. when the value set in the address detection register matches an address and the interrupt enab le bit is ?1?, the instruction code to be loaded into the cpu is forced to be replaced with the int9 instruction code. (1) register configuration (continued) address: 00009e h 76543210 pacsr bit r/w 0 r/w r/w r/w initial value read/write 000 program address detection control status register ad1e ad1d ad0e ad0d xxxx address: 001ff2 h 765432 10 program address detection register 0 (upper byte) padrh0 bit r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write 15 14 13 12 11 10 9 8 r/w x address: 001ff1 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x address: 001ff0 h 7 6 54 32 10 padrm0 padrl0 initial value read/write bit r/w x r/w r/w x r/w x r/w x r/w r/w r/w initial value read/write bit xxxx program address detection register 0 (middle byte) program address detection re gister 0 (lower byte) 15 14 13 12 11 10 9 8 r/w x address: 001ff5 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x padrh1 initial value read/write bit program address detection register 1 (upper byte) ? ? ? ? ? ? ? ?
mb90820 series 74 (continued) (2) block diagram address: 001ff4 h 76543 2 10 padrm1 bit r/w x r/w r/w x r/w x r/w x r/w r/w r/w initial value read/write xxxx 15 14 13 12 11 10 9 8 r/w x address: 001ff3 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x padrl1 initial value read/write bit program address detection register 1 (middle byte) program address detection register 1 (lower byte) address latch program address detection f 2 mc-16lx cpu int9 command comparator f 2 mc-16lx bus ad0e/ad1e ad0d/ad1d pacsr register 0/1
mb90820 series 75 15. rom mirroring function selection module the rom mirror function selection module sets the data in rom assigned to ff bank so that the data is read by access to 00 bank. (1) register configuration (2) block diagram 15 14 13 12 11 10 98 address : 00006f h romm 1 initial value bit r/w read/write rom mirror function selection register m1 x x x x x x x ? ? ? ? ? ? ? ? ? ? ? ? ? ? rom mirroring function rom 00 bank ff bank address area f 2 mc-16lx bus selection register
mb90820 series 76 16. 512k/1024k bits flash memory the 512k bits flash memory is allocated in the ff h banks on the cpu memory map. the 1024k bits flash memory is allocated in the fe h and ff h banks on the cpu memory map. like mask rom, flash memory is read-accessible and program-accessible to the cpu using the flash memory interface circuit. the flash memory can be programmed/ erased by the instruction from the cpu via the flash memory interface circuit. the flash memory can theref ore be reprogrammed (updated) while still on the circuit board under integrated cpu control, allowing pr ogram code and data to be improved efficiently. note that sector operations such as ?enable sector protect? cannot be used. features of 512k/1024k bits flash memory 64k 8 bits/32k 16 bits (32k + 8k 2 + 16k) sector configuration for 512k bits flash memory 128k 8 bits/64k 16 bits (64k + 32k + 8k 2 + 16k) sector configuration for 1024k bits flash memory automatic program algorithm (same as the embedded algorithm* : mbm29f400ta) installation of the deletion tempor ary stop/delete restart function write/delete completion detected by the data polling or toggle bit write/delete completion detected by the cpu interrupt compatibility with the jedec standard-type command each sector deletion can be executed (sectors can be freely combined) flash security function number of write/delete operati ons are guaranteed 10,000 times. * : embedded algorithm is a trademark of advanced micro devices, inc. (1) register configuration address: 0000ae h 76543210 flash memory control status register fmcs bit r/w 0 r/w 0 r/w 0 r x00 0 0 initial value read/write inte rdyint reserved reserved reserved reserved we rdy ????
mb90820 series 77 (2) sector configuration of flash memory the flash memory has the sector configuration illustrate d below. the addresses in the illustration are the upper and lower addresses of each sector. when 512k bits flash memory is accessed from the cpu, sa0 to sa3 are allocated in the ff bank. when 1024k bits flash memory is accessed from the cp u, sa0 to sa4 are allocate d in the fe and ff bank. * : the writer address is the address corresponding to the cpu address wh en writing data from a parallel flash memory writer. use the writer address when programm ing or erasing using a general-purpose parallel writer. sa3 (16k bytes) sa2 (8k bytes) sa1 (8k bytes) sa0 (32k bytes) flash memory cpu address *writer address ffffff h 7ffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fff h ff0000 h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h sa4 (16k bytes) sa3 (8k bytes) sa2 (8k bytes) sa1 (32k bytes) flash memory cpu address *writer address ffffff h 7ffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fff h ff0000 h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h sa0 (64k bytes) fe7fff h fe0000 h 6ffff h 60000 h
mb90820 series 78 electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : av cc must never exceed v cc when the power is turned on. *3 : v i and v o must never exceed v cc + 0.3 v. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : the maximum output current is a peak value for a corresponding pin. *5 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p4 7, p50, p51, p80 to p87. ? use within recommended operating conditions. ? use at dc voltage (current). ? the +b signal is an input signal exceeding v cc voltage. the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so t hat when the +b signal is applied the input current to the microcontroller pin does not exceed rated val ues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increas e the potential at the vcc pin, and this may affect other devices. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avr v ss ? 0.3 v ss + 6.0 v av cc avr, avr av ss input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma *5 total maximum clamp current | i clamp | ? 20 ma *5 ?l? level maximum output current i ol ? 15 ma *4 ?l? level average output current i olav1 ? 4 ma except for p00 to p07, p82 to p87 i olav2 ? 12 ma p00 to p07, p82 to p87 ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma ?h? level maximum output current i oh ?? 15 ma *4 ?h? level average output current i ohav ?? 4ma ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma power consumption p d ? 430 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb90820 series 79 ? note that if a +b signal is input when the microcontr oller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be su fficient to operate the power-on reset. ? care must be taken not to leave the +b input pin open. ? note that analog system input/output pins (lcd drive pins and comparator input pins, etc.) other than the a/d input pins cannot accept +b input. ? sample recommended circuits: warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. input/output equivalent circuits +b input (0 v to 16 v) limiting resistance protective diode vcc p-ch n-ch r
mb90820 series 80 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : uart ch0/1 data input pins p45/sin0, p72/sin1 /an10 can be used as cmos input by the communication prescaler control register (cdrr). *2 : use a ceramic capacitor or a capacitor with equivalent frequency char acteristics. on the v cc pin, connect a bypass capacitor that has a larger capacity than that of c s . refer to the following figure for connection of smoothing capacitor c s . parameter sym- bol pin name condi- tion value unit remarks min max power supply voltage v cc av cc ?? 4.5 5.5 v at normal operation t a = ? 40 c to + 85 c ?? 4.0 5.5 v normal operation when d/a converter is not used t a = ? 40 c to + 85 c ?? 3.5 5.5 v normal operation when a/d converter and d/a converter are not used t a = ? 40 c to + 85 c ?? 3.0 5.5 v maintains state in stop mode ?h? level input voltage v ih p30 to p37, p60 to p67 v cc = 5 v 10 % 0.7 v cc v cc + 0.3 v cmos input v ihs p00 to p07, p10 to p17 p20 to p27, p40 to p44, p45* 1 , p46, p47, p50, p51, p70, p71, p72* 1 , p73 to p77, p80 to p87, rst 0.8 v cc v cc + 0.3 v cmos hysteresis input v ihm md0, md1, md2 v cc ? 0.3 v cc + 0.3 v md input ?l? level input voltage v il p30 to p37, p60 to p67 v ss ? 0.3 0.3 v cc v cmos input v ils p00 to p07, p10 to p17 p20 to p27, p40 to p44, p45* 1 , p46, p47, p50, p51, p70, p71, p72* 1 , p73 to p77, p80 to p87 rst v ss ? 0.3 0.2 v cc v cmos hysteresis input v ilm md0, md1, md2 v ss ? 0.3 v ss + 0.3 v md input smoothing capacitor c s ?? 0.1 1.0 f*2 reference input voltage of a/d converter avr ?? 2.7 av cc v operating temperature t a ??? 40 + 85 c
mb90820 series 81 warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. c pin connection circuit c c s
mb90820 series 82 3. dc characteristics (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh all output pins v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol1 all pins except p00 to p07 p82 to p87 v cc = 4.5 v, i ol1 = 4.0 ma ?? 0.4 v v ol2 p00 to p07 p82 to p87 v cc = 4.5 v, i ol2 = 12.0 ma ?? 0.4 v input leakage current i il all input pins v cc = 5.5 v, v ss < v i < v cc ? 5 ? 5 a at pull-up disabled pull-up resistance r up p00 to p07 p10 to p17 p20 to p27 p30 to p37 rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? mask rom product
mb90820 series 83 (continued) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : the power supply current is regulated with an external clock. parameter symbol pin name condition value unit remarks min typ max power supply current* i cc v cc v cc = 5.0 v, internal frequency: 24 mhz, at normal operation ? 35 50 ma mask rom product ? 45 60 ma flash memory prod- uct v cc = 5.0 v, internal frequency: 24 mhz, at writing in flash memory ? 60 75 ma flash memory prod- uct v cc = 5.0 v, internal frequency: 24 mhz, at erasing memory ? 65 80 ma flash memory prod- uct i ccs v cc = 5.0 v, internal frequency: 24 mhz, at sleep mode ? 15 25 ma mask rom product ? ma flash memory prod- uct i cts v cc = 5.0 v, internal frequency: 2 mhz, at main timer mode ? 0.3 0.8 ma mask rom product ? ma flash memory prod- uct i cct v cc = 5.0 v, internal frequency: 8 mhz, at timer mode, t a = + 25 c ? 37 ma mask rom product ? a flash memory prod- uct i cch in stop mode, t a = + 25 c ? 520 ma mask rom product ? a flash memory prod- uct input capacitance c in except av cc , av ss , avr, c, v cc and v ss ?? 515pf
mb90820 series 84 4. ac characteristics (1) clock timings (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using oscillation circuit 3 ? 24 when using external clock 4 ? 24 1 multiplied pll 4 ? 12 2 multiplied pll 4 ? 8 3 multiplied pll 4 ? 6 4 multiplied pll 4 ? 4 6 multiplied pll clock cycle time t hcyl x0, x1 62.5 ? 333 ns when using oscillation circuit 41.67 ? 333 ns when using external clock input clock pulse width p wh p wl x0 10 ?? ns when using external clock, duty ratio is about 30% to 70%. input clock rise/fall time t cr t cf x0 ?? 5ns when using external clock internal operating clock frequency frequency f cp ? 1.5 ? 24 mhz internal operating clock cycle time t cp ? 41.67 ? 666 ns x 0 t hcyl t cf t cr 0.8 v c c 0.2 v c c p wh p wl
mb90820 series 85 the ac ratings are measured for the following measurement reference voltages operation guarantee range of pll power supply voltage v cc (v) normal operation guarantee range internal operating clock frequency f cp (mhz) relationship between internal operating clock frequency and power supply voltage relationship between cloc k frequency and internal operating clock frequency clock frequency f c (mhz) internal operating clock frequency f cp (mhz) not multiplied x4 24 4 1.5 5.5 3.5 4 12 16 24 3 4 8 16 1.5 8 4.5 4.0 12 guaranteed d/a conver ter operating range guaranteed a/d converter operating range 24 x6 x3 x2 x1 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pin pins other than hysteresis input/md input output signal waveform output pin
mb90820 series 86 (2) external reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. in the crystal oscillator, the oscillation time is between several ms to te ns of ms. in far/ceramic oscillator, the oscillation time is between hundreds of s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name value unit remarks min max reset input time t rstl rst 500 ? ns in normal operation oscillation time of oscillator* + 100 ? s in stop mode 100 ? s in timebase timer mode ? in normal operation mode ? in stop mode, at power on r st 0.2 v cc t rstl 0.2 v cc t rstl 0.2 v cc 0.2 v cc rst x0 internal operation clock oscillation time of oscillator 90 % of the oscillation amplitude 100 s oscillator stabilization time instruction execution internal reset
mb90820 series 87 (3) power-on reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden changes in the power suppl y voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, be sure to set the slope of rising within 50 mv/ms or less as shown below. parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply cut-off time t off v cc 1 ? ms waiting time for power supply on v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3 .0 v be sure to set the slope of rising within 50mv/ms or less. ram data hold time
mb90820 series 88 (4) uart0 and uart1 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? these are ac ratings in the clk synchronous mode. ? cl is the load capacitance value connected to pins while testing. ? t cp is machine cycle time (unit : ns). parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 8 t cp ? ns sck sot delay time t slov sck0 to sck1 sot0 to sot1 ? 80 + 80 ns valid sin sck t ivsh sck0 to sck1 sin0 to sin1 100 ? ns sck valid sin hold time t shix sck0 to sck1 sin0 to sin1 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of external shift clock mode 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck1 4 t cp ? ns sck sot delay time t slov sck0 to sck1 sot0 to sot1 ? 150 ns valid sin sck t ivsh sck0 to sck1 sin0 to sin1 60 ? ns sck valid sin hold time t shix sck0 to sck1 sin0 to sin1 60 ? ns
mb90820 series 89 sck sot sin sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb90820 series 90 (5) resources input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (6) trigger input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh t tiwl in0 to in3, tin0 to tin1, pwi0 to pwi1, dtti ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl int0 to int7 ? 5 t cp ? ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90820 series 91 5. a/d converter electrical characteristics (3.0 v avr ? av ss , v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avr = 5.0 v) note : the error increases proportionally as |avr - av ss | decreases. parameter symbol pin name value unit remarks min typ max resolution ?? ? 10 ? bit total error ?? ? ? 3.0 lsb non-linearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an15 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an15 avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb mv compare time ?? 1.0 ?? s4.5 v < avcc < 5.5 v 2.0 ?? s4.0 v < avcc < 4.5 v sampling time ?? 0.5 ?? s4.5 v < avcc < 5.5 v 1.2 ?? s4.0 v < avcc < 4.5 v analog port input current i ain an0 to an15 - 0.3 ? + 0.3 a analog input voltage v ain an0 to an15 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 2.4 4.7 ma i ah ?? 5 a* reference voltage supply current i r avr ? 600 900 a i rh ?? 5 a* offset between channels ? an0 to an15 ?? 4lsb
mb90820 series 92 6. a/d converter glossary resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a lin e across zero-transition line (?00 0000 0000? ? ?00 0000 0001?) and full-scale transition line (?11 1111 1110? ? ?11 1111 1111?) and actual conversion characteristics. differential linearity error : deviation of input voltage, wh ich is required for changing output code by 1 lsb, from an ideal value total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. (continued) 3ff h 3fe h 3 fd h 004 h 003 h 002 h 001 h avrl avrh v nt {1 lsb (n ? 1) + 0.5 lsb } 0.5 lsb 0.5 lsb total error actual conversion characteristics analog input total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avr ? avss 1024 [v] v ot (ideal value) = avss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] v nt : voltage at which of digital output transitions from (n ? 1) to n. actual conversion characteristics ideal characteristics (measurement value) digital output n : a/d converter digital output value
mb90820 series 93 (continued) 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h avss avr avss av r n + 1 n n ? 1 n ? 2 v nt v nt v (n + 1)t v ot v fst {1 lsb (n ? 1) + v ot } linearity error ideal characteristics (measurement value) digital output differential linearity error (measurement value) (measurement value) linearity error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which of digital output transmissions from ?000 h ? to ?001 h ?. v fst : voltage at which of digital output transmissions from ?3fe h ? to ?3ff h ?. actual conversion characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics (measurement value) (measurement value) digital output analog input analog input n : a/d converter digital output value
mb90820 series 94 7. notes on using a/d converter ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. and if the sampling time c annot be sufficient, connect a capacitor of about 0.1 mf to the analog input pin. about the error the accuracy gets worse as | avr ? av ss | becomes smaller. r c rc mb90822/823 2.0 k ? (max) 14.4 pf (max) MB90F822A/f823a 2.0 k ? (max) 16.0 pf (max) ? analog input circuit model analog input during sampling : on comparator note : the values are reference values. MB90F822A/f823a mb90822/ 823 0 5 10 15 20 25 30 3 5 0 10 20 30 40 50 60 70 80 90 1 00 MB90F822A/f823a mb90822/ 823 01234567 8 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] ? the relationship between the external impedance and minimum sampling time
mb90820 series 95 8. electrical characteristics of d/a convertor (v cc = av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : with load capacitance 20 pf. parameter symbol pin name condition value unit remarks min typ max resolution ?? ? ? 8 ? bit differential linearity error ?? ?? 0.5 lsb conversion time ?? ? 0.45 ? s* analog output impedance ?? ? 2.9 3.8 k ? power supply current i dvr av cc ? 160 920 a i dvrs ? 0.1 ? a d/a stops
mb90820 series 96 9. flash memory program/erase characteristics * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . ordering information parameter condition value unit remarks min typ max sector erase time t a = +25 c v cc = 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16 bit width) programing time ? 16 3,600 s except for the overhead time of the system program/erase cycle ? 10,000 ?? cycle flash data retention time average t a = +85 c 20 ?? year * part number package remarks mb90f823apfv MB90F822Apfv mb90822pfv mb90823pfv 80-pin plastic lqfp (fpt-80p-m05) mb90f823apfm MB90F822Apfm mb90822pfm mb90823pfm 80-pin plastic lqfp (fpt-80p-m11) mb90f823apf MB90F822Apf mb90822pf mb90823pf 80-pin plastic qfp (fpt-80p-m06)
mb90820 series 97 package dimensions (continued) 80-pin plastic qfp (fpt-80p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins th ickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parenth eses are reference values. c 2002 fujitsu limited f80010s-c-6-5 1 24 25 40 41 64 65 80 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.80(.031) 0.370.05 (.015.002) m 0.16(.006) "a" 0.170.06 (.007.002) 0.10(.004) 0.800.20 (.031.008) 0.880.15 (.035.006) 0~8 ? .120 ?.008 +.012 ?0.20 +0.30 3.05 0.25(.010) 0.30 +0.10 ?0.25 +.004 ?.010 .012 (stand off) details of "a" part (mounting height) * *
mb90820 series 98 (continued) 80-pin plastic lqfp (fpt-80p-m11) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins th ickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parenth eses are reference values. c 2003 fujitsu limited f80016s-c-3-6 120 21 40 61 80 41 60 14.000.10(.551.004)sq 16.000.20(.630.008)sq index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" (.006.002) 0.1450.055 0.10(.004) 0.500.20 (.020.008) 0.600.15 (.024.006) 0~8 ? .059 ?.004 +.008 ?0.10 +0.20 1.50 (mounting height) 0.25(.010) 0.100.10 (.004.004) (stand off) details of "a" part *
mb90820 series 99 (continued) 80-pin plastic lqfp (fpt-80p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins th ickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parenth eses are reference values. c 2003 fujitsu limited f80008s-c-4-8 120 40 21 60 41 80 61 index 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) "a" 0 ? ~8 ? .059 ?.004 +.008 ?0.10 +0.20 1.50 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (stand off) 0.25(.010) details of "a" part lead no. (mounting height) *
mb90820 series the information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/mic roelectronics/product/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0510 ? 2005 fujitsu limited printed in japan

▲Up To Search▲

Price & Availability of MB90F822A

	To Download MB90F822A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .